VHDL design flow using Terminal for Xilinx ISE 14.7 and Spartan 6 FPGA

Here I would like to present the CLI or Terminal based flow of VHDL design and synthesis using Ubuntu 12.04 local network server and Xilinx ISE 14.7 building scripts. Assuming Xilinx ISE installed correctly and PATH env variable is configured by original shell script –
source /opt/Xilinx/path_to_ise/settings64.sh

Also make sure you have installed libusb-dev and all necessary drivers for USB Cable programmer to work fully fine!

Build Generics
Makefile

SHELL := /bin/bash

# Spartan 6 LX9, TQG144 Package, XC6SLX9-TQG144
PART := xc6slx9-tqg144-3

# Top-level module name
TOP := top

# Source and constraint files
SRCS := $(TOP).vhd
# TB_SRCS := top_tb.v -- use if needed to have
UCF := pinout.ucf
PRJ := $(TOP).prj
XST_SCRIPT := $(TOP).xst

# Output files
NGC := $(TOP).ngc
NGD := $(TOP).ngd
MAP_NCD := $(TOP)_map.ncd
PCF := $(TOP).pcf
ROUTED_NCD := $(TOP)_routed.ncd
BIT := $(TOP).bit
BTMMAP := $(TOP).bmm

.PHONY: all help synth translate map par bitgen prog sim prj xst clean distclean flash

all: bitgen

help:
    @echo "Available targets:"
    @echo " make all"        - build bitstream ($(BIT))"
    @echo " make synth.      - run XST synthesis"
    @echo " make translate   - run NGDBUILD"
    @echo " make map         - run MAP"
    @echo " make par         - run PAR"
    @echo " make bitgen      - generate bitstream"
    @echo " make sim         - run VHDL simulation"
    @echo " make prog        - open iMPACT in batch mode using impact.cmd"
    @echo " make clean.      - remove generated build files"
    @echo " make distclean   - remove generated files plus auto-creates scripts"
    @echo " make flash       - flash SPI W25Q64BV 8MByte SPI Flash to make bit file permanent"
    @echo ""
    @echo "Edit these variables if needed"
    @echo " TOP=$(TOP)"
    @echo " PART=$(PART)"
    @echo " SRCS=$(SRC)
    @echo " UCF=$(UCF)"

$PRJ: $(SRCS)
         @rm -f $(PRJ)
         @for f in $(SRCS); do echo "vhdl work $$f" >> $(PRJ); done

$(XST_SCIRPT): $(PRJ)
          @print '%s\n' \
                 "run" \
                 "-ifn $(PRJ)" \
                 "-ifmt mixed" \
                 "-top $(TOP)" \
                 "-ofn $(TOP)" \
                 "-ofmt NGC" \
                 "-p $(PART)" \
                 > $(XST_SCRIPT)

synth: $(NGC)

$(NGC): $(SRCS) $(PRJ) $(XST_SCRIPT)
        xst -ifn $(XST_SCRIPT)

translate: $(NGD)

$(NGD): $(NGC) $(UCF)
        ngdbuild -uc $(UCF) -p $(PART) $(NGC) $(NGD)

map: $(MAP_NCD)

$(MAP_NCD): $(NGD)
        map -p $(PART) -o $(MAP_NCD) $(NGD) $(PCF)

par: $(ROUTED_NCD)

$(ROUTED_NCD): $(MAP_NCD) $(PCF)
        par -w $(MAP_NCD) $(ROUTED_NCD) $(PCF)

bitgen: $(BIT)

$(BIT): $(ROUTED_NCD)
        bitgen -w $(ROUTED_NCD) $(BIT)

sim:
        @echo "Simulation implementation not done. Please add your code here"

prog: $(BIT)
        impact -batch impact.cmd

flash:
        impact -batch flash.cmd

clean:
        rm -f xst.log xst.xrpt
        rm -f ngdbuild.log map.log par.log bitgen.log
        rm -f *.b *.drc *.lso *.map *.mrp *.ncd *.ngc *.ngd *.ngr *.pad
        rm -f *.par *.pcf *.ptwx *.srp *.bgn *.bin *.bit *.cmd_log *.html *.xml
        rm -f *.xrpt *.xpi *.xwbt *.twx *.txt *_envsettings.html usage_statistics_webtalk.html
        rm -f simv a.out # for simulation files

distclean: clean
        rm -f $(PRJ) $(XST_SCRIPT)

top.prj

vhdl work "top.vhd"
# vhdl work other_modules.vhd
# Add all your files

top.xst

run
-ifn top.prj
-ifmt mixed
-top top
-ofn top
-ofmt NGC
-p xc6slx9-tqg144-3

imapct.cmd

setMode -bscan
setCable -p auto
identify
assignFile -p 1 -file top.bit
program -p 1
quit

promgen.sh

#!/bin/bash

echo "Generating MCS PROM File for Board QSPI Flash - W25Q64BV Flash IC"

promgen -w -p mcs -c FF top.mcs -s 8192 -u 0000 top.bit -spi